Threefish-256 algorithm implementation on reconfigurable hardware
DOI:
https://doi.org/10.15332/iteckne.v11i2.725Keywords:
Cryptographic, FPGA, synchronous design, Threefish, VHDLAbstract
This article presents both the description and results of the Threefish cryptographic algorithm hardware implementation for encryption process. The implementation of the algorithm was performed by using the iterative round architecture on the FPGA (Field Programmable Gate Array) Virtex-5 present in the development system XUPV5-LX110T. Place and route results show that the design Threefish-256 iterative round has a throughput of 551Mbps.
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