Design methodology using FPGA in a course on digital systems

Authors

  • José Luis Uribe Aponte Hewlett-Packard Company
  • Alejandra María González Correal Pontificia Universidad Javeriana
  • Alejandro Forero Guzmán Pontificia Universidad Javeriana
  • Juan Carlos Giraldo Carvajal Pontificia Universidad Javeriana
  • Francisco Fernando Viveros Moreno Pontificia Universidad Javeriana

DOI:

https://doi.org/10.15332/iteckne.v9i1.2752

Keywords:

Project based learning, Digital systems design, Design methodology

Abstract

This paper present a methodology for the design of digital systems on FPGA (Field Programmable Gate Array). The proposed methodology offers a guide from initial stages of analysis of customer needs until the final implementation in a programmable device. The methodology has been applied and validated in courses of Digital Systems Design in Electronic Engineering Program at Pontificia Universidad Javeriana - Bogotá, following a model of PBL (Project Based Learning) allowing students to achieve a significant learning in technical issues, increasing their level of motivation toward engineering and enhancing their communication skills, teamwork and design capabilities. This is the result of research during the last four years in engineering education, developed by the group of professors of Digital Electronics.

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Author Biographies

José Luis Uribe Aponte, Hewlett-Packard Company

MSc. en Ciencias de la Computación, Universidad de los Andes. ASIC Engineer, HP Networking Hewlett-Packard Company, Costa Rica

Alejandra María González Correal, Pontificia Universidad Javeriana

MSc. en Ingeniería Electrónica, Ph.D (c) en Ingeniería. Investigador Grupo MIMESIS, Pontificia Universidad Javeriana, Bogotá, Colombia

Alejandro Forero Guzmán, Pontificia Universidad Javeriana

MSc. en Ingeniería Electrónica, Ph.D (c) en Ingeniería. Investigador Grupo SIRP, Pontificia Universidad Javeriana, Bogotá, Colombia

Juan Carlos Giraldo Carvajal, Pontificia Universidad Javeriana

MSc. en Ingeniería Electrónica,Pontificia Universidad Javeriana. Docente Tiempo Completo Pontificia Universidad Javeriana, Bogotá, Colombia

Francisco Fernando Viveros Moreno, Pontificia Universidad Javeriana

Ingeniero Electrónico. Profesor Titular de Tiempo Completo. Director del Grupo de Investigación MIMESIS. Jefe de la Sección de Técnicas Digitales, Pontificia Universidad Javeriana, Bogotá, Colombia

References

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Published

2014-11-26

How to Cite

Uribe Aponte, J. L., González Correal, A. M., Forero Guzmán, A., Giraldo Carvajal, J. C., & Viveros Moreno, F. F. (2014). Design methodology using FPGA in a course on digital systems. ITECKNE, 9(1), 107–114. https://doi.org/10.15332/iteckne.v9i1.2752

Issue

Section

Academic Discussion Articles