Threefish-256 algorithm implementation on reconfigurable hardware
Keywords:
Cryptographic, FPGA, synchronous design, Threefish, VHDL
Abstract
This article presents both the description and results of the Threefish cryptographic algorithm hardware implementation for encryption process. The implementation of the algorithm was performed by using the iterative round architecture on the FPGA (Field Programmable Gate Array) Virtex-5 present in the development system XUPV5-LX110T. Place and route results show that the design Threefish-256 iterative round has a throughput of 551Mbps.
Downloads
Download data is not yet available.
References
[1] D. Stinson, Cryptography: Theory and Practice, Third Edit. CRC Press, Inc, 2005.
[2] B. Schneier, N. Ferguson, and S. Lucks, “The skein hash function family,” Submission to NIST (Round 3), 2010. [Online]. Available: http://www.skein-hash.info/sites/default/files/skein1.3.pdf.
[3] NIST, “Cryptographic hash algorithm competition,” National Institute of Standards and Technology, 2005. [Online]. Available: http://csrc.nist.gov/groups/ST/hash/sha-3/index.html.
[4] NIST, “Tentative Timeline of the Development of New Hash Functions,” National Institute of Standards and Technology, 12-Jul-2006. [Online]. Available: http://csrc.nist.gov/groups/ST/hash/timeline.html.
[5] NIST, “Announcing request for candidate algorithm nominations for a new cryptographic hash algorithm (SHA-3) Family,” Federal Register, 29-Oct-2007. [Online]. Available: https://federalregister.gov/a/E7- 21581.
[6] Xilinx, “Virtex-5 FPGA Data Sheet,” Xilinx Inc., 2009. [Online]. Available: http://www.xilinx.com/support/documentation/data_sheets/ds202.pdf.
[7] Xilinx, “Xilinx UG190 Virtex-5 FPGA User Guide,” Xilinx Inc., 16-Mar-2012. [Online]. Available: http://www.xilinx.com/support/documentation/user_guides/ug190.pdf.
[8] M. Liskov, R. L. Rivest, and D. Wagner, “Tweakable block ciphers,” J. Cryptol., vol. 24, no. 3, pp. 588–613, Sep. 2011.
[9] N. Ferguson, S. Lucks, B. Schneier, D. Whiting, M. Bellare, T. Kohno, J. Callas, and J. Walker, “The Skein Hash Function Family,” Schneier on Security, 01-Nov-2008. [Online]. Available: https://www.schneier.com/skein.html.
[10] N. At, J. L. Beuchat, and I. San, “Compact implementation of threefish and Skein on FPGA,” in 2012 5th International Conference on New Technologies, Mobility and Security - Proceedings of NTMS 2012 Conference and Workshops, 2012, pp. 1–5.
[11] M. Long, “Implementing skein hash function on xilinx virtex-5 fpga platform,” 02-Feb-2009. [Online]. Available: http://www.skein-hash.info/sites/default/files/skein_fpga.pdf.
[12] A. H. Namin and M. A. Hasan, “Hardware Implementation of the Compression Function for Selected SHA-3 Candidates,” CACR 2009-28, 2009. [Online]. Available: http://cacr.uwaterloo.ca/techreports/2009/cacr2009-28.pdf.
[13] J. Walker, F. Sheikh, S. Mathew, and R. Krishnamurthy, “A Skein-512 Hardware Implementation,” Aug-2010. [Online]. Available: http://csrc.nist.gov/groups/ST/hash/sha-3/Round2/Aug2010/documents/papers/WALKER_skein-intel-hwd.pdf.
[14] A. Schorr, “Performance analysis of a scalable hardware fpga skein implementation,” Kate Gleason College of Engineering, Rochester Institute of Technology, Rochester, NY, 2010.
[15] S. Tillich, “Hardware Implementation of the SHA-3 Candidate Skein.,” IACR Cryptology ePrint Archive, Apr-2009. [Online]. Available: http://eprint.iacr.org/2009/159.pdf?origin=publication_detail.
[16] B. Jungk and J. Apfelbeck, “Area-Efficient FPGA Implementations of the SHA-3 Finalists,” in 2011 International Conference on Reconfigurable Computing and FPGAs, 2011, pp. 235–241.
[2] B. Schneier, N. Ferguson, and S. Lucks, “The skein hash function family,” Submission to NIST (Round 3), 2010. [Online]. Available: http://www.skein-hash.info/sites/default/files/skein1.3.pdf.
[3] NIST, “Cryptographic hash algorithm competition,” National Institute of Standards and Technology, 2005. [Online]. Available: http://csrc.nist.gov/groups/ST/hash/sha-3/index.html.
[4] NIST, “Tentative Timeline of the Development of New Hash Functions,” National Institute of Standards and Technology, 12-Jul-2006. [Online]. Available: http://csrc.nist.gov/groups/ST/hash/timeline.html.
[5] NIST, “Announcing request for candidate algorithm nominations for a new cryptographic hash algorithm (SHA-3) Family,” Federal Register, 29-Oct-2007. [Online]. Available: https://federalregister.gov/a/E7- 21581.
[6] Xilinx, “Virtex-5 FPGA Data Sheet,” Xilinx Inc., 2009. [Online]. Available: http://www.xilinx.com/support/documentation/data_sheets/ds202.pdf.
[7] Xilinx, “Xilinx UG190 Virtex-5 FPGA User Guide,” Xilinx Inc., 16-Mar-2012. [Online]. Available: http://www.xilinx.com/support/documentation/user_guides/ug190.pdf.
[8] M. Liskov, R. L. Rivest, and D. Wagner, “Tweakable block ciphers,” J. Cryptol., vol. 24, no. 3, pp. 588–613, Sep. 2011.
[9] N. Ferguson, S. Lucks, B. Schneier, D. Whiting, M. Bellare, T. Kohno, J. Callas, and J. Walker, “The Skein Hash Function Family,” Schneier on Security, 01-Nov-2008. [Online]. Available: https://www.schneier.com/skein.html.
[10] N. At, J. L. Beuchat, and I. San, “Compact implementation of threefish and Skein on FPGA,” in 2012 5th International Conference on New Technologies, Mobility and Security - Proceedings of NTMS 2012 Conference and Workshops, 2012, pp. 1–5.
[11] M. Long, “Implementing skein hash function on xilinx virtex-5 fpga platform,” 02-Feb-2009. [Online]. Available: http://www.skein-hash.info/sites/default/files/skein_fpga.pdf.
[12] A. H. Namin and M. A. Hasan, “Hardware Implementation of the Compression Function for Selected SHA-3 Candidates,” CACR 2009-28, 2009. [Online]. Available: http://cacr.uwaterloo.ca/techreports/2009/cacr2009-28.pdf.
[13] J. Walker, F. Sheikh, S. Mathew, and R. Krishnamurthy, “A Skein-512 Hardware Implementation,” Aug-2010. [Online]. Available: http://csrc.nist.gov/groups/ST/hash/sha-3/Round2/Aug2010/documents/papers/WALKER_skein-intel-hwd.pdf.
[14] A. Schorr, “Performance analysis of a scalable hardware fpga skein implementation,” Kate Gleason College of Engineering, Rochester Institute of Technology, Rochester, NY, 2010.
[15] S. Tillich, “Hardware Implementation of the SHA-3 Candidate Skein.,” IACR Cryptology ePrint Archive, Apr-2009. [Online]. Available: http://eprint.iacr.org/2009/159.pdf?origin=publication_detail.
[16] B. Jungk and J. Apfelbeck, “Area-Efficient FPGA Implementations of the SHA-3 Finalists,” in 2011 International Conference on Reconfigurable Computing and FPGAs, 2011, pp. 235–241.
Published
2014-12-31
How to Cite
Nieto-Ramírez, N., & Nieto-Londoño, R. (2014). Threefish-256 algorithm implementation on reconfigurable hardware. ITECKNE, 11(2), 149-156. https://doi.org/https://doi.org/10.15332/iteckne.v11i2.725
Issue
Section
Research and Innovation Articles
